1. Field of the Invention
This invention relates to field-effect transistors (FETs), MOS (Metal Oxide Semiconductor) devices, and MOS-gate modulation doped field-effect transistors (MODFETs) in which the gate consists of a layer or layer(s) of cladded nanoparticles or cladded quantum dots. The device structure behaves as fast access nonvolatile memory structure or as a FET exhibiting multiple states (such as three-state) in its drain current-gate voltage characteristics depending on the configuration of the layers in the gate region which consists layers of cladded quantum dots and thin insulating films. In particular, MOS gate quantum dot nonvolatile memory and 3-state devices in MODFET structural configuration are described. MODFET configured as self-aligned MOS gate incorporating QD layers in gate and asymmetric couple well transport channels is one of the embodiments described for fast access nonvolatile memories. This invention also describes basic cells using quantum dot (QD) gate nonvolatile memory devices, in either QD gate FET or QD gate MODFET configuration, functioning as nonvolatile random access memory (RAM) with appropriate access transistors and bit line architecture. The QD gate FET based nonvolatile RAM (NVRAM) will replace a dynamic random access memory (DRAM) without the need of refreshing or maintaining biasing. Using a multi-bit QD gate nonvolatile memory device, a multi-bit NVRAM is envisioned. In addition, various configurations of static RAMs (SRAMs) using 3-state QD gate FETs are described. Use of 3-state n-channel and p-channel QD FETs configured as SRAM cells are shown to result in 3 state or 4-state memory operations.
2. Brief Description of Prior Art
Nonvolatile memories are used to store information in microchips in flash memory and nonvolatile random access memory [NVRAM] configurations [Sharma, 2003]. Floating trap memory [realized as SONOS (Si-Oxide-Nitride-Oxide-Si) structures] and floating gate memories are two generally used configurations for nonvolatile ROM, EEPROM and flash memories [Brown and Brewer (1998) and Cappelletti et al. (1999)]. Another important category is nonvolatile random access memories (RAMs) which are generally realized as dynamic RAMs (DRAMs; these include magnetic RAMs (MRAMs), carbon nanotube based, and ferroelectric RAM devices), and nonvolatile static RAMs (SRAMs) [Sharma, 2003]. In the case of SRAMs, nonvolatile devices are connected in parallel to conventional SRAM cells. More recently carbon nanotube based memories, where the state of carbon nanotube depends on the gate operating conditions, are reported. These memory devices are continually being scaled down to smaller sizes (such as sub 100 nm) with fast access time and smaller operating voltages. FIG. 1(a) and FIG. 1(b) show schematically two floating gate nonvolatile memory with regular and asymmetric source and drain regions. FIG. 1(c-1, to c-3) describes Read, Program or Write, and Erase operation in NOR configuration. FIG. 2(a) and FIG. 2(b) show schematically front and back-gated floating trap SONOS nonvolatile memory structures, respectively. There are many structural and process variations, as well as circuit architectures (such as NOR and NAND) in designing the floating gate and floating trap nonvolatile memories.
Nonvolatile floating gate quantum dot memories (QDMs), shown in FIGS. 3(a) and 3(b), represent another class of nonvolatile memories that are reported in the literature [Tiwari et al (1995, 1996), and Hasaneen et al (2004)]. In quantum dot gate nonvolatile memories, the charge may be discretely localized on the quantum dots if they are separated from each other. Thus, the charge distribution on the floating quantum dots is not continuous like conventional floating gate devices, and is determined by the tunneling of carriers (either directly from channel or via hot carriers from the drain end or source end). FIG. 3(a) shows a quantum dot gate memory first proposed by Tiwari et al.(1995) FIG. 3(b) shows a strained layer Si transport channel which is fabricated on a SiGe layer [Hasannen et al 2004] to obtain desired carrier mobility in the transport channel. Other investigators including Ostraat et al.[2001] have reported floating gate memory structures using Si nanocrystals. Ostraat et al. have summarized the advantages of nanocrystal based charge storage including: 1) reduced punch-through by reducing drain to floating gate coupling, 2) reduction in stress induced leakage currents, and 3) potentially enhanced retention times. However, the conventional QD based nonvolatile memory suffers from small retention time and fluctuations of electrical characteristics. In the current quantum dot gate device processing there is little control over the location of Si nanoparticles in the gate, their sizes, as well as the separation between them. Invariably, these Si nanocrystal dots are not cladded they touch each other. Some reports outlining formation of cladding on self-organized dots is in the literature after the dots are created. Here, they again suffer from the dot size variation problem inherent in conventional fabrication techniques including those employ self-organization.
Jain [2008] in U.S. patent application Ser. No. 12/006,974 has described quantum dot (QD) gate nonvolatile memories (QDMs) and 3-state FETs using cladded quantum dots. Here, cladded quantum dots (with appropriate diameter Si core is cladded with an insulator such as SiOx) are assembled or deposited on the transport channel of a FET forming the floating gate. The cladding maintains a sufficient separation between Si nanodots. Along with a thin tunnel and control gate layers, the structures control the channel to dot tunneling and inter-dot tunneling, thus improving the ‘write and read’ and the retention time characteristics. In addition, layers of self-assembled SiOx—Si quantum dots provide discrete values of charge at the floating gate that in turn results in multiple values of threshold shifts suitable for multiple-bit ‘Program’ and ‘Read’ capability. This patent describes various QD-gate FETs in Si and other substrates (such as GaAs, InP, etc.) for nonvolatile memory and 3-state FET structures. In addition, the use of coupled-quantum well transport channel, which has more than one wells and appropriate number of barrier layers, is presented for improved device performance. FIGS. 4-6 describe some QD-gate nonvolatile memory structures, and FIG. 7 describes a 3-state FET device.
In this invention, we describe a circuit configuration which permits use of QD-gate nonvolatile memories functioning as random access memories (RAMs) where periodic refreshing like DRAMs is not needed. What is also described in this application is the use of QD gate MODFET structures which are potentially faster than conventional QD gate FETs. In particular, MOS-gate Si MODFETs as memory and 3-state FETs are described. Three layers of quantum dots in the gate may result in two intermediate states (overall 4-states) in MODFET devices presented here.